The present invention relates to an integrated circuit arrangement and method for the manufacture thereof.
The question of planarity is increasingly gaining in significance in the realization of integrated circuit arrangements having high packing density and, in particular, having structural sizes below 0.25 μm. In the manufacture of the integrated circuit arrangements, useful structures that have a circuit-oriented function in the circuit arrangement are generated on a semiconductor substrate. Such useful structures are, for example, terminal electrodes, gate electrodes or interconnects. These useful structures are respectively manufactured in planes by structuring a previously produced layer. Insulation layers are provided between successive planes. These insulation layers are planarized by polishing and/or etching.
The planarity that can be achieved when planarizing layers is thereby dependent on the geometrical density of the useful structures in the respective plane. Given an extremely non-uniform occupation with useful structures, large spaces locally derive wherein irregularities occur in the planarization process. It has therefore been proposed (see, for example, D. Widmann, H. Mader, H. Friedrich Technologie Hochintegrierter Schaltungen, 2nd Edition, Springer-Verlag, 1996, pages 346 through 347) to insert filling structures between the useful structures that have no circuit-oriented function but that nonetheless increase the local geometrical density. As a result thereof, a uniform occupation in the respective plane is assured, this enabling a higher planarity following planarization steps.
When the useful structures and the filler structures are composed of conductive material, then a charging of the filler structures can occur during operation. In order to avoid this, the filler structures are applied to a fixed potential, as disclosed in Widmann, et al. This contacting to a fixed potential ensues via specific wiring arranged in a metallization plane above the useful and filler structures. This additional wiring and the contacts between the additional wiring and the filler structures make production of the layout more difficult.